Modeling instruction decoders (WS 2023-2024)
Instruction decoders are common components in system-on-chips models. They occur as elements of instruction set simulators as well as processor toolchains. The arduous and error-prone process of manual decoder design can be greatly aided by the automated generation of decoders from high-level descriptions. Unfortunately, automation is hindered by the growing complexity of instruction sets. The seminar will explore various approaches to automatically generate efficient instruction decoders. The work includes an oral presentation and a written elaboration of the topic. Each participant is expected to present a recent paper from the Robocup Symposium. Participation in the oral presentations of other participants is also required. The procedure is according to the implementation rules of the faculty.
Registration: via email until 08.10.2023, 23:59 Uhr
Kick-off event: probably week 42, announcement via Moodle after registration period.
Number of participants: 6-8 persons