About the block practical course
The following topics will be covered:
- Acquiring the language basics of VHDL (language constructs, data types etc.)
- Modeling of simple logic operations as well as special logic circuits in VHDL using
- logic circuits in VHDL with the help of behavioral and structural descriptions based on basic logic gates and state machines
- Creating complex digital circuits, e.g. a CPU by combining different logic circuits
- Creation of test environments for simulation and verification of the modeled circuits
- Graphical visualization of the modeled state machines and systems
After successful completion of the lab, students will have acquired a good knowledge of language constructs, data types, and how VHDL works. They are able to model a wide variety of digital logic circuits using VHDL based on basic gates and state machines, and also to emulate complex circuit designs such as ALUs and simple CPUs. Furthermore, you will be able to verify and evaluate the function of your models using self-generated test environments.
Block practical course
The block practical course will be held in German.
Lecturers: Aaron Larisch, Diana Kleingarn
- 15.08.2022 - 26.08.2022, each from 09.00 - 15.00 hrs.
- Location: Retina-Pool IRF 111
- The practical course takes place at the beginning of the lecture-free period of the summer semester.
Registration and allocation of places
- Registration period: 18.04.2022 - 15.05.2022
- Registration via LSF
- The number of participants is limited to 15. In case of cancellations, the next students can register.
- Master students have priority over Bachelor students
Current information in connection with the event (dates) will be published exclusively via Moodle. Furthermore, the Moodle workspace with its various communication possibilities (chat, mailing lists, forum, etc.) is used for collaborative work in the context of the event.
Interested students please register in the LSF. Only participants who have registered in the LSF will be automatically transferred from the LSF to the Moodle workspace. For further announcements in the context of the event, Moodle will be used exclusively.
For the subject "Simulation of Digital Circuits in VHDL", students must complete the following examinations:
- Successful completion of 70% of the internship tasks.
Successful completion of these tasks confirms successful participation in the internship. Grades are not awarded.
- Scope: practical laboratory course 2 weeks (block)
- Credits: 3
- Event number 08 0055
- 1st semester in Master ET/IT
- Module Praktikum 5, ETIT-215 for ET/IT, AR-316 for A&R